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DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 3 days ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
ICECCS
1995
IEEE
100views Hardware» more  ICECCS 1995»
13 years 9 months ago
POSD-a notation for presenting complex systems of processes
When trying to describe the behaviour of large systems, such as the business processes of large enterprises, we often adopt diagramming techniques based on derivatives of data flo...
Peter Henderson, Graham D. Pratten
SIMVIS
2003
13 years 7 months ago
An Experimental Study of the Behaviour of the Proxel-Based Simulation Algorithm
The paradigm of the proxel ("probability element") was recently introduced in order to provide a new algorithmic approach to analysing discrete-state stochastic models s...
Sanja Lazarova-Molnar, Graham Horton
ENTCS
2006
146views more  ENTCS 2006»
13 years 5 months ago
Relating State-Based and Process-Based Concurrency through Linear Logic
This paper has the purpose of reviewing some of the established relationships between logic and concurrency, and of exploring new ones. Concurrent and distributed systems are noto...
Iliano Cervesato, Andre Scedrov
ISPD
2003
ACM
89views Hardware» more  ISPD 2003»
13 years 11 months ago
Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning
Traditional multilevel partitioning approaches have shown good performance with respect to cutsize, but offer no guarantees with respect to system performance. Timing-driven part...
Andrew B. Kahng, Xu Xu