43 search results - page 9 / 9 » Physical Synthesis for CPLD Architectures |
DATE
2007
IEEE
13 years 12 months ago
2007
IEEE
Alcatel Alenia Space is deeply involved in the Galileo program at many stages. In particular, Alcatel Alenia Space has successfully designed and delivered the very first navigatio...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
DAC
2005
ACM
13 years 7 months ago
2005
ACM
This paper presents a novel placement algorithm for timing optimization based on a new and powerful concept, which we term differential timing analysis. Recognizing that accurate ...