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DAC
2005
ACM
13 years 7 months ago
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
Ho Young Kim, Tag Gon Kim
IPPS
1998
IEEE
13 years 9 months ago
Register-Sensitive Software Pipelining
In this paper, we propose an integrated approach for register-sensitive software pipelining. In this approach, the heuristics proposed in the stage scheduling method of Eichenberg...
Amod K. Dani, V. Janaki Ramanan, Ramaswamy Govinda...
ISCC
2003
IEEE
13 years 10 months ago
Pipelined Maximal Size Matching Scheduling Algorithms for CIOQ Switches.
In this paper, we propose new pipelined request-grant-accept (RGA) and request-grant (RG) maximal size matching (MSM) algorithms to achieve speedup in combined input and output qu...
Mei Yang, Si-Qing Zheng
PLDI
2005
ACM
13 years 10 months ago
Register allocation for software pipelined multi-dimensional loops
Software pipelining of a multi-dimensional loop is an important optimization that overlaps the execution of successive outermost loop iterations to explore instruction-level paral...
Hongbo Rong, Alban Douillet, Guang R. Gao
AC
2004
Springer
13 years 4 months ago
The Timeboxing process model for iterative software development
In today's business where speed is of essence, an iterative development approach that allows the functionality to be delivered in parts has become a necessity and an effectiv...
Pankaj Jalote, Aveejeet Palit, Priya Kurien