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» Pipelined FPGA Adders
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FPL
2010
Springer
168views Hardware» more  FPL 2010»
11 years 11 months ago
Pipelined FPGA Adders
Integer addition is a universal building block, and applications such as quad-precision floating-point or elliptic curve cryptography now demand precisions well beyond 64 bits. Thi...
Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasc...
FPGA
1998
ACM
131views FPGA» more  FPGA 1998»
12 years 5 months ago
Managing Pipeline-Reconfigurable FPGAs
Srihari Cadambi, Jeffrey Weener, Seth Copen Goldst...
FPGA
2011
ACM
393views FPGA» more  FPGA 2011»
11 years 5 months ago
Comparing FPGA vs. custom cmos and the impact on processor microarchitecture
As soft processors are increasingly used in diverse applications, there is a need to evolve their microarchitectures in a way that suits the FPGA implementation substrate. This pa...
Henry Wong, Vaughn Betz, Jonathan Rose
GLVLSI
2003
IEEE
195views VLSI» more  GLVLSI 2003»
12 years 7 months ago
A pipelined clock-delayed domino carry-lookahead adder
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
Bhushan A. Shinkre, James E. Stine
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