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FPL
2010
Springer

Pipelined FPGA Adders

11 years 9 months ago
Pipelined FPGA Adders
Integer addition is a universal building block, and applications such as quad-precision floating-point or elliptic curve cryptography now demand precisions well beyond 64 bits. This study explores the trade-offs between size, latency and frequency for pipelined large-precision adders on FPGA. It compares three pipelined adder architectures: the classical pipelined ripple-carry adder, a variation that reduces register count, and an FPGAspecific implementation of the carry-select adder capable of providing lower latency additions at a comparable price. For each of these architectures, resource estimation models are defined, and used in an adder generator that selects the best architecture considering the target FPGA, the target operating frequency, and the addition bit width. Keywords-addition; pipeline; low-latency; FPGA
Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasc
Added 11 Feb 2011
Updated 11 Feb 2011
Type Journal
Year 2010
Where FPL
Authors Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasca
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