192 search results - page 1 / 39 » Pipelined FPGA Adders |
FPL
2010
Springer
13 years 2 months ago
2010
Springer
Integer addition is a universal building block, and applications such as quad-precision floating-point or elliptic curve cryptography now demand precisions well beyond 64 bits. Thi...
FPGA
1999
ACM
13 years 8 months ago
1999
ACM
FPGA
1998
ACM
13 years 8 months ago
1998
ACM
FPGA
2011
ACM
12 years 8 months ago
2011
ACM
As soft processors are increasingly used in diverse applications, there is a need to evolve their microarchitectures in a way that suits the FPGA implementation substrate. This pa...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...