10 search results - page 1 / 2 » Polynomial Abstraction for Verification of Sequentially Impl... |
DATE
2004
IEEE
13 years 10 months ago
2004
IEEE
ASPDAC
2001
ACM
13 years 10 months ago
2001
ACM
Abstract- Traditional state-traversal-basedmethods for verifying sequential circuits are computationally infeasible for circuits with a large number of memory elements. However, if...
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
Methods for performing component matching by expressing an arithmetic specification and a bit-level description of an implementation as word-level polynomials have been demonstrat...
ICCAD
2002
IEEE
14 years 3 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
If real number calculations are implemented as circuits, only a limited preciseness can be obtained. Hence, formal verification can not be used to prove the equivalence between th...