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    » Post-Layout Optimization for Deep Submicron Design
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    DAC
    1996
    ACM
    81views Computer Architecture» more  DAC 1996»
    Post-Layout Optimization for Deep Submicron Design
    13 years 9 months ago
    Post-Layout Optimization for Deep Submicron Design
    Download  www.cs.york.ac.uk
    To reduce the number of synthesis and layout iterations, we present a new delay optimization technique, which inserts buers based on back-annotated detailed routing information. D...
    Koichi Sato, Masamichi Kawarabayashi, Hideyuki Emu...
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    DAC
    1996
    ACM
    119views Computer Architecture» more  DAC 1996»
    VAMP: A VHDL-Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic Systems
    13 years 9 months ago
    VAMP: A VHDL-Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic Systems
    Download  www.cs.york.ac.uk
    This paper presents a new concept for accurate modeling and timing simulationof electronicsystems integrated in a typical VHDL design environment, taking into account the requirem...
    Bernhard Wunder, Gunther Lehmann, Klaus D. Mü...
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    ISPD
    1998
    ACM
    88views Hardware» more  ISPD 1998»
    An efficient technique for device and interconnect optimization in deep submicron designs
    13 years 9 months ago
    An efficient technique for device and interconnect optimization in deep submicron designs
    Download  cadlab.cs.ucla.edu
    In this paper, we formulate a new class of optimization problem, named the general CH-posynomial program, and reveal the general dominance property. We propose an efcient algorith...
    Jason Cong, Lei He
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    HPCA
    2002
    IEEE
    152views Distributed And Parallel Com...» more  HPCA 2002»
    Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
    14 years 5 months ago
    Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
    Download  www.ece.cmu.edu
    Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
    Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....
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    ISLPED
    1997
    ACM
    86views Hardware» more  ISLPED 1997»
    Device and technology optimizations for low power design in deep sub-micron regime
    13 years 9 months ago
    Device and technology optimizations for low power design in deep sub-micron regime
    Download  www.cs.berkeley.edu
    Kai Chen 0002, Chenming Hu
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