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» Postsilicon Validation Methodology for Microprocessors
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CODES
2001
IEEE
13 years 9 months ago
Development cost and size estimation starting from high-level specifications
This paper addresses the problem of estimating cost and development effort of a system, starting from its complete or partial high-level description. In addition, some modificatio...
William Fornaciari, Fabio Salice, Umberto Bondi, E...
ICCAD
2003
IEEE
135views Hardware» more  ICCAD 2003»
13 years 10 months ago
ATPG for Noise-Induced Switch Failures in Domino Logic
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
Rahul Kundu, R. D. (Shawn) Blanton
DAC
1999
ACM
13 years 9 months ago
IC Test Using the Energy Consumption Ratio
Dynamic-current based test techniques can potentially address the drawbacks of traditional and Iddq test methodologies. The quality of dynamic current based test is degraded by pr...
Wanli Jiang, Bapiraju Vinnakota
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 2 months ago
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques
— The need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. Embedded and highperformance mic...
Xiaoyao Liang, Kerem Turgay, David Brooks
PATMOS
2007
Springer
13 years 11 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...