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» Potential Slack Budgeting with Clock Skew Optimization
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ICCAD
2010
IEEE
166views Hardware» more  ICCAD 2010»
13 years 3 months ago
Low-power clock trees for CPUs
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a l...
Dongjin Lee, Myung-Chul Kim, Igor L. Markov
ICCAD
2004
IEEE
127views Hardware» more  ICCAD 2004»
14 years 2 months ago
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
DAC
2008
ACM
13 years 7 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Min Ni, Seda Ogrenci Memik
ICCAD
1999
IEEE
86views Hardware» more  ICCAD 1999»
13 years 9 months ago
Clock skew scheduling for improved reliability via quadratic programming
This paper considers the problem of determining an optimal clock skew schedule for a synchronous VLSI circuit. A novel formulation of clock skew scheduling as a constrained quadrat...
Ivan S. Kourtev, Eby G. Friedman
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
14 years 3 days ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...