46 search results - page 9 / 10 » Power Estimation of Cell-Based CMOS Circuits |
ISLPED
1997
ACM
13 years 9 months ago
1997
ACM
Significand pre-alignment is a pre requisite for floating point additions. This paper1 addresses the architectural design and energy delay evaluation of a Low Power Barrel Switch ...
GLVLSI
2007
IEEE
13 years 8 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
DSN
2005
IEEE
13 years 12 months ago
2005
IEEE
It is now widely accepted that the CMOS technology implementing irreversible logic will hit a scaling limit beyond 2016, and that the increased power dissipation is a major limiti...
DAC
2004
ACM
13 years 10 months ago
2004
ACM
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...
MICRO
2010
IEEE
13 years 4 months ago
2010
IEEE
Bias temperature instability, hot-carrier injection, and gate-oxide wearout will cause severe lifetime degradation in the performance and the reliability of future CMOS devices. Th...