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» Power minimization derived from architectural-usage of VLIW ...
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DAC
2000
ACM
13 years 9 months ago
Power minimization derived from architectural-usage of VLIW processors
Catherine H. Gebotys, Robert J. Gebotys, S. Wiratu...
ISVLSI
2006
IEEE
150views VLSI» more  ISVLSI 2006»
13 years 11 months ago
Design and Analysis of a Low Power VLIW DSP Core
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
Chan-Hao Chang, Diana Marculescu
CAMP
2005
IEEE
13 years 6 months ago
Energy/Performance Evaluation of the Multithreaded Extension of a Multicluster VLIW Processor
Abstract— In this paper we address the problem of the architectural exploration from the energy/performance point of view of a VLIW processor for embedded systems. We also consid...
Domenico Barretta, Gianluca Palermo, Mariagiovanna...
TVLSI
2002
102views more  TVLSI 2002»
13 years 4 months ago
Low-power data forwarding for VLIW embedded architectures
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
Mariagiovanna Sami, Donatella Sciuto, Cristina Sil...
INFOCOM
2002
IEEE
13 years 9 months ago
Adaptive Load Sharing for Network Processors
—A novel scheme for processing packets in a router is presented that provides load sharing among multiple network processors distributed within the router. It is complemented by ...
Lukas Kencl, Jean-Yves Le Boudec