24 search results - page 3 / 5 » Power optimizations for transport triggered SIMD processors |
CHES
2007
Springer
13 years 11 months ago
2007
Springer
Abstract. This paper discusses the state-of-the-art fast software implementation of block ciphers on Intel’s new microprocessor Core2, particularly concentrating on “bitslice i...
VLSISP
2008
13 years 5 months ago
2008
Many different video processor architectures exist. Its architecture gives a processor strength for a particular application. Hardwired logic yields the best performance/cost, but ...
ICASSP
2011
IEEE
12 years 9 months ago
2011
IEEE
In this paper, we investigate the opportunities offered by floatingpoint arithmetics in enabling an assembly and intrinsics free highlevel language based development. We compare ...
MICRO
2002
IEEE
13 years 10 months ago
2002
IEEE
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...