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ISCAS
2005
IEEE
103views Hardware» more  ISCAS 2005»
13 years 11 months ago
Why area might reduce power in nanoscale CMOS
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
Paul Beckett, S. C. Goldstein
EMSOFT
2010
Springer
13 years 3 months ago
Energy-aware packet and task co-scheduling for embedded systems
A crucial objective in battery operated embedded systems is to work under the minimal power consumption that provides a desired level of performance. Dynamic Voltage Scaling (DVS)...
Luca Santinelli, Mauro Marinoni, Francesco Prosper...
SIES
2007
IEEE
13 years 11 months ago
Process Oriented Power Management
— Though modern operating systems have a capable of controlling the power consumption using the DVFS (Dynamic Voltage and Frequency Scaling) mechanism, it is controlled for some ...
Daisuke Miyakawa, Yutaka Ishikawa
ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
13 years 10 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
DATE
2010
IEEE
148views Hardware» more  DATE 2010»
13 years 10 months ago
Scalable stochastic processors
Abstract—Future microprocessors increasingly rely on an unreliable CMOS fabric due to aggressive scaling of voltage and frequency, and shrinking design margins. Fortunately, many...
Sriram Narayanan, John Sartori, Rakesh Kumar, Doug...