6 search results - page 1 / 2 » Power variations of multi-port routers in an application-spe... |
ICCD
2007
IEEE
13 years 11 months ago
2007
IEEE
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...
HPCA
2008
IEEE
14 years 5 months ago
2008
IEEE
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
CSREAESA
2006
13 years 6 months ago
2006
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. As technology scales to deep sub-...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
Networks-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP core...