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» Power-aware slack distribution for hierarchical VLSI design
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ISCAS
2005
IEEE
115views Hardware» more  ISCAS 2005»
13 years 10 months ago
Power-aware slack distribution for hierarchical VLSI design
Abstract— Hierarchical design plays an important role in microprocessor and ASIC domains where design complexity limits design productivity and tool capacity. Slack distribution,...
Hyung-Ock Kim, Youngsoo Shin
VLSID
1998
IEEE
112views VLSI» more  VLSID 1998»
13 years 9 months ago
Web-based Distributed VLSI Design
Emerging "systems-on-a-chip" will require a design environment that allows distributed access to libraries, models and design tools. In this paper we present a framework...
Debashis Saha, Anantha Chandrakasan
VLSID
2005
IEEE
98views VLSI» more  VLSID 2005»
14 years 5 months ago
False Path and Clock Scheduling Based Yield-Aware Gate Sizing
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
CASES
2003
ACM
13 years 8 months ago
A hierarchical approach for energy efficient application design using heterogeneous embedded systems
Several features such as reconfiguration, voltage and frequency scaling, low-power operating states, duty-cycling, etc. are exploited for latency and energy efficient application ...
Sumit Mohanty, Viktor K. Prasanna
ICPP
2000
IEEE
13 years 9 months ago
Multilayer VLSI Layout for Interconnection Networks
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-l...
Chi-Hsiang Yeh, Emmanouel A. Varvarigos, Behrooz P...