223 search results - page 3 / 45 » Practical algorithms for performance guarantees in buffered ... |
ICC
2008
IEEE
13 years 11 months ago
2008
IEEE
—A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with i...
INFOCOM
2006
IEEE
13 years 11 months ago
2006
IEEE
— Three-stage non-blocking switching fabrics are the next step in scaling current crossbar switches to many hundreds or few thousands of ports. Congestion (output contention) man...
ICCCN
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract— The switch architecture with the combined inputcrosspoint queueing (CICQ) scheme has been recognized as a practical promising solution for building cost-effective highp...
HOTI
2002
IEEE
13 years 10 months ago
2002
IEEE
We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input- and crosspoint-queued structure with virtual output...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...