20 search results - page 4 / 4 » Practical techniques to reduce skew and its variations in bu... |
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
ICCAD
2007
IEEE
14 years 2 months ago
2007
IEEE
— Clock meshes posses inherent low clock skews and excellent immunity to PVT variations, and have increasingly found their way to high-performance IC designs. However, analysis o...
CODES
2006
IEEE
13 years 11 months ago
2006
IEEE
Embedded system optimization typically considers objectives such as cost, timing, buffer sizes and power consumption. Robustness criteria, i.e. sensitivity of the system to variat...
EMSOFT
2007
Springer
13 years 11 months ago
2007
Springer
Design space exploration of embedded systems typically focuses on classical design goals such as cost, timing, buffer sizes, and power consumption. Robustness criteria, i.e. sensi...
ICDCS
2011
IEEE
12 years 5 months ago
2011
IEEE
Abstract—Wireless Sensor Networks (WSNs) are increasingly available for mission-critical applications such as emergency management and health care. To meet the stringent requirem...