28 search results - page 1 / 6 » Pragmatic integrated scheduling for clustered VLIW architect... |
SPE
2008
13 years 5 months ago
2008
CF
2004
ACM
13 years 11 months ago
2004
ACM
Centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption and are thus not suitable for consumer electronic devices. The conse...
IEEEPACT
2000
IEEE
13 years 10 months ago
2000
IEEE
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...
EMSOFT
2006
Springer
13 years 9 months ago
2006
Springer
Miniaturization of devices and the ensuing decrease in the threshold voltage has led to a substantial increase in the leakage component of the total processor energy consumption. ...
ICCD
2003
IEEE
14 years 2 months ago
2003
IEEE
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...