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» Precomputation-based Guarding for Dynamic and Leakage Power ...
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ISQED
2007
IEEE
140views Hardware» more  ISQED 2007»
13 years 11 months ago
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation o...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...
DAC
2005
ACM
14 years 6 months ago
A novel synthesis approach for active leakage power reduction using dynamic supply gating
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 5 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
ICCD
2007
IEEE
322views Hardware» more  ICCD 2007»
14 years 2 months ago
Voltage drop reduction for on-chip power delivery considering leakage current variations
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sourc...
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
14 years 2 months ago
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction
Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduc...
Feng Gao, John P. Hayes