492 search results - page 98 / 99 » Predictable performance in SMT processors |
HPCA
2008
IEEE
14 years 5 months ago
2008
IEEE
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
CC
2010
Springer
13 years 11 months ago
2010
Springer
On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...
ICS
2003
Tsinghua U.
13 years 10 months ago
2003
Tsinghua U.
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
IPCCC
1999
IEEE
13 years 9 months ago
1999
IEEE
Performance evaluation of modern, highly speculative, out-of-order microprocessors and the corresponding production of detailed, valid, accurate results have become serious challe...
CORR
2006
Springer
13 years 4 months ago
2006
Springer
The decision tree is one of the most fundamental ing abstractions. A commonly used type of decision tree is the alphabetic binary tree, which uses (without loss of generality) &quo...