33 search results - page 3 / 7 » Predicting MPI Buffer Addresses |
SAC
2006
ACM
13 years 11 months ago
2006
ACM
Modern embedded processors access the Branch Target Buffer (BTB) every cycle to speculate branch target addresses. Such accesses, quite often, are unnecessary as there is no branc...
INFOCOM
1993
IEEE
13 years 9 months ago
1993
IEEE
This paper addresses the problem of finding the worst case end-to-end delay and buffer occupancy bounds in ATM networks with rate-controlled, non-work conserving servers. A theore...
ICCD
2002
IEEE
14 years 2 months ago
2002
IEEE
We introduce Branch Predictor Prediction (BPP) as a power-aware branch prediction technique for high performance processors. Our predictor reduces branch prediction power dissipat...
ASPLOS
2009
ACM
14 years 6 months ago
2009
ACM
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
ISQED
2002
IEEE
13 years 10 months ago
2002
IEEE
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...