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2006
ACM

Branchless cycle prediction for embedded processors

9 years 1 months ago
Branchless cycle prediction for embedded processors
Modern embedded processors access the Branch Target Buffer (BTB) every cycle to speculate branch target addresses. Such accesses, quite often, are unnecessary as there is no branch instruction among those fetched. In this work we introduce Branchless Cycle Prediction (BLCP) to exploit this design inefficiency. BLCP uses a simple power efficient structure to predict cycles where there is no branch instruction among those fetched, at least one cycle in advance. We avoid accessing BTB during such cycles. We show that, by using BLCP, it is possible to reduce BTB power dissipation by 32% while paying a negligible performance cost (average: 0.2%). Categories and Subject Descriptors
Kaveh Jokar Deris, Amirali Baniasadi
Added 14 Jun 2010
Updated 14 Jun 2010
Type Conference
Year 2006
Where SAC
Authors Kaveh Jokar Deris, Amirali Baniasadi
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