4 search results - page 1 / 1 » Preserving HDL synthesis hierarchy for cell placement |
ISPD
1997
ACM
13 years 9 months ago
1997
ACM
ISPD
1998
ACM
13 years 9 months ago
1998
ACM
In this paper, we present a performance-driven softmacro clustering and placement method which preserves HDL design hierarchy to guide the soft-macro placement process. We also pr...
DAC
1997
ACM
13 years 9 months ago
1997
ACM
In this paper, we present a new integrated synthesis and partitioning method for multiple-FPGA applications. This method rst synthesizes a design speci cation in a ne-grained way ...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and efficient heuristics for placing the cells in a bit-s...