18 search results - page 2 / 4 » Probabilistic maximum error modeling for unreliable logic ci... |
MICRO
2006
IEEE
13 years 4 months ago
2006
IEEE
Shrinking devices to the nanoscale, increasing integration densities, and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. Frequent oc...
CSL
2010
Springer
13 years 4 months ago
2010
Springer
We study probabilistic complexity classes and questions of derandomisation from a logical point of view. For each logic L we introduce a new logic BPL, bounded error probabilistic ...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
A probabilistic power estimation technique for combinational circuits is presented. A novel set of simple waveforms is the kernel of this technique. The transition density of each...
TVLSI
2008
13 years 4 months ago
2008
Abstract--The quantum-dot cellular automata (QCA) model offers a novel nano-domain computing architecture by mapping the intended logic onto the lowest energy configuration of a co...
TCAD
1998
13 years 4 months ago
1998
—This paper addresses, from a probabilistic point of view, the issue of switching activity estimation in combinational circuits under the zero-delay model. As the main theoretica...