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» Process Variation Aware Issue Queue Design
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DATE
2008
IEEE
119views Hardware» more  DATE 2008»
14 years 5 months ago
Process Variation Aware Issue Queue Design
In sub-90nm process technology it becomes harder to control the fabrication process, which in turn causes variations between the design-time parameters and the fabricated paramete...
Raghavendra K, Madhu Mutyam
DSN
2008
IEEE
14 years 5 months ago
Analysis and solutions to issue queue process variation
The last few years have witnessed an unprecedented explosion in transistor densities. Diminutive feature sizes have enabled microprocessor designers to break the billion-transisto...
Niranjan Soundararajan, Aditya Yanamandra, Chrysos...
ASPDAC
2004
ACM
96views Hardware» more  ASPDAC 2004»
14 years 2 months ago
Mixed-clock issue queue design for energy aware, high-performance cores
- Globally-Asynchronous, Locally-Synchronous (GALS) design style has started to gain interest recently as a possible solution to the increased design complexity, power and thermal ...
Venkata Syam P. Rapaka, Emil Talpes, Diana Marcule...
DAC
2006
ACM
14 years 11 months ago
Process variation aware OPC with variational lithography modeling
Optical proximity correction (OPC) is one of the most widely used resolution enhancement techniques (RET) in nanometer designs to improve subwavelength printability. Conventional ...
Peng Yu, Sean X. Shi, David Z. Pan
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
14 years 4 months ago
Instruction packing: reducing power and delay of the dynamic scheduling logic
The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for...
Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghos...