51 search results - page 9 / 11 » Process Variation Tolerant 3T1D-Based Cache Architectures |
MICRO
2010
IEEE
13 years 16 days ago
2010
IEEE
Since the non-cache parts of a core are less regular, compared to on-chip caches, tolerating manufacturing defects in the processing core is a more challenging problem. Due to the ...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
—Static and dynamic variations, which have negative impact on the reliability of microelectronic systems, increase with smaller CMOS technology. Thus, further downscaling is only...
CASES
2008
ACM
13 years 7 months ago
2008
ACM
While technology advances have made MPSoCs a standard architecture for embedded systems, their applicability is increasingly being challenged by dramatic increases in the amount o...
MIDDLEWARE
2004
Springer
13 years 11 months ago
2004
Springer
The Internet provides a wealth of useful information in a vast number of dynamic information sources, but it is difficult to determine which sources are useful for a given query. ...
VLSID
2003
IEEE
14 years 6 months ago
2003
IEEE
In this paper we present statistical timing driven hMetisbased partitioning. We approach timing driven partitioning from a different perspective: we use the statistical timing cri...