15 search results - page 3 / 3 » Process variation aware thread mapping for Chip Multiprocess... |
FPGA
2007
ACM
13 years 10 months ago
2007
ACM
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
LCTRTS
2010
Springer
13 years 11 months ago
2010
Springer
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
ISQED
2009
IEEE
13 years 11 months ago
2009
IEEE
—As device feature size continues to shrink, reliability becomes a severe issue due to process variation, particle-induced transient errors, and transistor wear-out/stress such a...
HIPEAC
2009
Springer
13 years 7 months ago
2009
Springer
Shrinking process technologies and growing chip sizes have profound effects on process variation. This leads to Chip Multiprocessors (CMPs) where not all cores operate at maximum f...
ISPASS
2010
IEEE
13 years 11 months ago
2010
IEEE
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...