Sciweavers

63 search results - page 2 / 13
» Process variation robust clock tree routing
Sort
View
ISPD
2003
ACM
106views Hardware» more  ISPD 2003»
13 years 10 months ago
Process variation aware clock tree routing
Bing Lu, Jiang Hu, Gary Ellis, Haihua Su
ASPDAC
2006
ACM
158views Hardware» more  ASPDAC 2006»
13 years 11 months ago
Process-induced skew reduction in nominal zero-skew clock trees
— This work develops an analytic framework for clock tree analysis considering process variations that is shown to correspond well with Monte Carlo results. The analysis framewor...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...
ICCAD
2010
IEEE
141views Hardware» more  ICCAD 2010»
13 years 3 months ago
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, ...
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 9 months ago
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield
Abstract-- Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we propose minimum clo...
Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh ...
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
14 years 2 months ago
Statistical based link insertion for robust clock network design
We present a statistical based non-tree clock distribution construction algorithm that starts with a tree and incrementally insert cross links, such that the skew variation of the...
Wai-Ching Douglas Lam, J. Jam, Cheng-Kok Koh, Venk...