Sciweavers

40 search results - page 2 / 8
» Process variation tolerant low power DCT architecture
Sort
View
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
13 years 11 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
ICIP
2003
IEEE
14 years 6 months ago
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores
For motion estimation (ME) and discrete cosine transform (DCT) of MPEG video encoding, content variation and perceptual tolerance in video signals can be exploited to gracefully t...
Andrew Laffely, Jian Liang, Russell Tessier, Wayne...
ASPDAC
2007
ACM
122views Hardware» more  ASPDAC 2007»
13 years 8 months ago
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications
- The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low ...
Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan
ISLPED
2009
ACM
154views Hardware» more  ISLPED 2009»
13 years 9 months ago
Experimental analysis of sequence dependence on energy saving for error tolerant image processing
We present experimental analysis to exploit the sequence dependence on energy saving in error tolerant image processing. Our analysis shows that the error distributions depend not...
Se Hun Kim, Saibal Mukhopadhyay, Wayne Wolf
ISCA
2008
IEEE
135views Hardware» more  ISCA 2008»
13 years 11 months ago
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...
Xiaoyao Liang, Gu-Yeon Wei, David Brooks