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ASPDAC
2001
ACM
104views Hardware» more  ASPDAC 2001»
13 years 8 months ago
Processor-programmable memory BIST for bus-connected embedded memories
Abstract--We present a processor-programmable built-in selftest (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circ...
Ching-Hong Tsai, Cheng-Wen Wu
INTEGRATION
1998
96views more  INTEGRATION 1998»
13 years 4 months ago
BIST for systems-on-a-chip
An increasing part of microelectronic systems is implemented on the basis of predesigned and preverified modules, so-called cores, which are reused in many instances. Core-provide...
Hans-Joachim Wunderlich
MTDT
2003
IEEE
105views Hardware» more  MTDT 2003»
13 years 10 months ago
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu L...
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
14 years 5 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
ASPDAC
2000
ACM
96views Hardware» more  ASPDAC 2000»
13 years 8 months ago
A programmable built-in self-test core for embedded memories
Testing embedded memories is becoming an industry-wide concern with the advent of deep-submicron technology and system-on-chip applications. We present a prototype chip for a progr...
Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu