43 search results - page 1 / 9 » Processor-time-optimal systolic arrays |
ICPP
1991
IEEE
13 years 8 months ago
1991
IEEE
This paper presents an architecture for programmable systolic arrays that provides simple and e cient systolic communication. The Brown Systolic Array is a linear implementation o...
FDL
2003
IEEE
13 years 10 months ago
2003
IEEE
Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the...
APCSAC
2006
IEEE
13 years 10 months ago
2006
IEEE
The systolic array paradigm has low communication demand because it does not use costly global communication and each processor communicates with few other processors. It is thus s...
BIBE
2007
IEEE
13 years 11 months ago
2007
IEEE
Systolic implementations of dynamic programming solutions that utilize a similarity matrix can achieve appreciable performance with both course- and fine-grain parallelization. A ...
IPPS
1998
IEEE
13 years 9 months ago
1998
IEEE
The paper presents the design of a hardware genetic algorithm which uses a pipeline of systolic arrays. Demostrated is the design methodology, where a simple genetic algorithm exp...