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SYNASC
2005
IEEE
117views Algorithms» more  SYNASC 2005»
13 years 11 months ago
Functional-Based Synthesis of Systolic Online Multipliers
— Systolic online algorithms for the multiplication of univariate polynomials and of multiple precision integers are synthesised using a novel method based on the following funct...
Tudor Jebelean, Laura Szakacs
ASAP
2008
IEEE
186views Hardware» more  ASAP 2008»
13 years 11 months ago
Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs
RNA structure prediction, or folding, is a computeintensive task that lies at the core of several search applications in bioinformatics. We begin to address the need for high-thro...
Arpith C. Jacob, Jeremy Buhler, Roger D. Chamberla...
ISCAS
2006
IEEE
70views Hardware» more  ISCAS 2006»
13 years 11 months ago
A systolic array technique for determining common approximate substrings
— A new technique that makes use of a systolic array structure is proposed for solving the common approximate substring (CAS) problem. This approach extends the technique introdu...
Kenneth B. Kent, Jacqueline E. Rice
ISCAS
2002
IEEE
91views Hardware» more  ISCAS 2002»
13 years 10 months ago
Pipelined RLS adaptive architecture using relaxed Givens rotations (RGR)
In this paper, we focus on developing a new relaxed Givens rotations (RGR)-RLS algorithm and the corresponding RGR-RLS systolic array. The resulting algorithm and architecture pos...
Lan-Da Van, Chih-Hong Chang
IPPS
1999
IEEE
13 years 9 months ago
FPGA Implementation of Modular Exponentiation
An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs...
Alexander Tiountchik, Elena Trichina