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ASPDAC
2007
ACM
83views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency
Subhasis Banerjee, G. Surendra, S. K. Nandy
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
13 years 10 months ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...
EMSOFT
2004
Springer
13 years 10 months ago
Binary translation to improve energy efficiency through post-pass register re-allocation
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
Kun Zhang, Tao Zhang, Santosh Pande
ISPASS
2008
IEEE
13 years 11 months ago
Program Phase Detection based on Critical Basic Block Transitions
Many programs go through phases as they execute. Knowing where these phases begin and end can be beneficial. For example, adaptive architectures can exploit such information to lo...
Paruj Ratanaworabhan, Martin Burtscher
CGO
2005
IEEE
13 years 10 months ago
Effective Adaptive Computing Environment Management via Dynamic Optimization
To minimize the surging power consumption of microprocessors, adaptive computing environments (ACEs) where microarchitectural resources can be dynamically tuned to match a program...
Shiwen Hu, Madhavi Gopal Valluri, Lizy Kurian John