Sciweavers

19 search results - page 1 / 4
» Programmable LDPC Decoder Based on the Bubble-Sort Algorithm
Sort
View
VLSID
2006
IEEE
158views VLSI» more  VLSID 2006»
13 years 11 months ago
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
ISCAS
2007
IEEE
141views Hardware» more  ISCAS 2007»
13 years 11 months ago
Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes
Abstract— We analyze the decoding algorithm for regular timeinvariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which...
Emil Matús, Marcos B. S. Tavares, Marcel Bi...
DATE
2009
IEEE
170views Hardware» more  DATE 2009»
13 years 11 months ago
A novel LDPC decoder for DVB-S2 IP
Abstract—In this paper a programmable Forward Error Correction (FEC) IP for a DVB-S2 receiver is presented. It is composed of a Low-Density Parity Check (LDPC), a Bose-ChaudhuriH...
Stefan Müller 0004, Manuel Schreger, Marten K...
ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
13 years 10 months ago
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
In-Cheol Park, Se-Hyeon Kang
ICASSP
2008
IEEE
13 years 11 months ago
High-performance scheduling algorithm for partially parallel LDPC decoder
In this paper, we propose a new scheduling algorithm for the overlapped message passing decoding, which can be applied to general low-density parity check (LDPC) codes. The partia...
Cheng-Zhou Zhan, Xin-Yu Shih, An-Yeu Wu