Sciweavers

28 search results - page 2 / 6
» Putting Faulty Cores to Work
Sort
View
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
14 years 7 days ago
Architectural core salvaging in a multi-core processor for hard-error tolerance
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
Michael D. Powell, Arijit Biswas, Shantanu Gupta, ...
PDP
2010
IEEE
14 years 14 days ago
Scheduling Metric-Space Queries Processing on Multi-Core Processors
Abstract—This paper proposes a strategy to organize metricspace query processing in multi-core search nodes as understood in the context of search engines running on clusters of ...
Veronica Gil Costa, Ricardo J. Barrientos, Maurici...
VL
2003
IEEE
139views Visual Languages» more  VL 2003»
13 years 11 months ago
Strategies and behaviors of end-user programmers with interactive fault localization
End-user programmers are writing an unprecedented number of programs, due in large part to the significant effort put forth to bring programming power to end users. Unfortunately,...
Shrinu Prabhakararao, Curtis R. Cook, Joseph R. Ru...
HOTI
2008
IEEE
14 years 1 days ago
Network Processing on an SPE Core in Cell Broadband Engine
Cell Broadband EngineTM is a multi-core system on a chip and is composed of a general-purpose Power Processing Element (PPE) and eight Synergistic Processing Elements (SPEs). Its ...
Yuji Kawamura, Takeshi Yamazaki, Hiroshi Kyusojin,...
ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
13 years 11 months ago
Rescue: A Microarchitecture for Testability and Defect Tolerance
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
Ethan Schuchman, T. N. Vijaykumar