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» Quadratic placement using an improved timing model
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DATE
2004
IEEE
151views Hardware» more  DATE 2004»
9 years 28 days ago
Boosting: Min-Cut Placement with Improved Signal Delay
In this work we improve top-down min-cut placers in the context of timing closure. Using the concept of boosting factors, we adjust net weights according to net spans, so as to re...
Andrew B. Kahng, Igor L. Markov, Sherief Reda
ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
9 years 6 months ago
Placement Driven Retiming with a Coupled Edge Timing Model
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...
Ingmar Neumann, Wolfgang Kunz
ISPD
2003
ACM
171views Hardware» more  ISPD 2003»
9 years 2 months ago
Timing driven force directed placement with physical net constraints
This paper presents a new timing driven force directed placement algorithm that meets physical net length constraints as well as constraints on specific pin sets. It is the first ...
Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tu...
IPPS
2007
IEEE
9 years 3 months ago
Miss Ratio Improvement For Real-Time Applications Using Fragmentation-Aware Placement
Partially reconfigurable Field-Programmable Gate Arrays (FPGAs) allow parts of the chip to be configured at run-time where each part could hold an independent task. Online place...
Ahmed Abou ElFarag, Hatem M. El-Boghdadi, Samir I....
DATE
2008
IEEE
204views Hardware» more  DATE 2008»
9 years 3 months ago
Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis
Shrinking feature sizes and process variations are of increasing concern in modern technology. It is urgent that we develop statistical interconnect timing models which are harmon...
Jun-Kuei Zeng, Chung-Ping Chen
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