2057 search results - page 2 / 412 » Quadratic placement using an improved timing model |
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
In this work we improve top-down min-cut placers in the context of timing closure. Using the concept of boosting factors, we adjust net weights according to net spans, so as to re...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
This paper presents a new timing driven force directed placement algorithm that meets physical net length constraints as well as constraints on specific pin sets. It is the first ...
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
Partially reconfigurable Field-Programmable Gate Arrays (FPGAs) allow parts of the chip to be configured at run-time where each part could hold an independent task. Online place...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Shrinking feature sizes and process variations are of increasing concern in modern technology. It is urgent that we develop statistical interconnect timing models which are harmon...