13 search results - page 2 / 3 » Quantitative analysis of transaction level models for the AM... |
DAC
2004
ACM
13 years 10 months ago
2004
ACM
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
Efficient communication modeling is a critical task in SoC design and exploration. In particular, fast and accurate communication is needed to predict the performance of a system....
ISQED
2006
IEEE
13 years 11 months ago
2006
IEEE
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
In this paper we present a generic interconnect fabric for transaction level modelling tackeling three major aspects. First, a review of the bus and IO structures that we have ana...
FDL
2007
IEEE
13 years 11 months ago
2007
IEEE
Transaction level models (TLMs) can be constructed at t levels of abstraction, denoted as untimed (UT), cycle-approximate (CX), and cycle accurate (CA) in this paper. The choice o...