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» Quasi-Resonant Interconnects: A Low Power Design Methodology
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VTS
2005
IEEE
95views Hardware» more  VTS 2005»
13 years 10 months ago
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...
Baosheng Wang, Yuejian Wu, Josh Yang, André...
BMCBI
2006
128views more  BMCBI 2006»
13 years 5 months ago
Rank-statistics based enrichment-site prediction algorithm developed for chromatin immunoprecipitation on chip experiments
Background: High density oligonucleotide tiling arrays are an effective and powerful platform for conducting unbiased genome-wide studies. The ab initio probe selection method emp...
Srinka Ghosh, Heather A. Hirsch, Edward A. Sekinge...
SBCCI
2003
ACM
129views VLSI» more  SBCCI 2003»
13 years 10 months ago
Hyperspectral Images Clustering on Reconfigurable Hardware Using the K-Means Algorithm
Unsupervised clustering is a powerful technique for understanding multispectral and hyperspectral images, being k-means one of the most used iterative approaches. It is a simple th...
Abel Guilhermino S. Filho, Alejandro César ...
DAC
2005
ACM
14 years 6 months ago
User-perceived latency driven voltage scaling for interactive applications
Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level voltage scaling techniques, such as...
Le Yan, Lin Zhong, Niraj K. Jha