147 search results - page 3 / 30 » Queue Machines: Hardware Compilation in Hardware |
FPGA
2010
ACM
13 years 4 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows...
FPL
2001
Springer
13 years 9 months ago
2001
Springer
This paper presents new achievements on the automatic mapping of algorithms, written in imperative software programming languages, to custom computing machines. The reconfigurable ...
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
Building an optimising compiler is a difficult and time consuming task which must be repeated for each generation of a microprocessor. As the underlying microarchitecture changes...
ICCD
2000
IEEE
14 years 1 months ago
2000
IEEE
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...