4 search results - page 1 / 1 » RAPPID: An Asynchronous Instruction Length Decoder |
ASYNC
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving As...
DAC
1999
ACM
14 years 6 months ago
1999
ACM
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
ASPDAC
2001
ACM
13 years 9 months ago
2001
ACM
Abstract-- In order to continue to produce circuits of increasing speeds, designers must consider aggressive circuit design styles such as self-resetting or delayed-reset domino ci...