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» RT-Level ITC'99 Benchmarks and First ATPG Results
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DT
2000
162views more  DT 2000»
13 years 4 months ago
RT-Level ITC'99 Benchmarks and First ATPG Results
Effective high-level ATPG tools are increasingly needed, as an essential element in the quest for reducing as much as possible the designer work on gate-level descriptions. We pro...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
VTS
2000
IEEE
108views Hardware» more  VTS 2000»
13 years 9 months ago
High-Level Observability for Effective High-Level ATPG
This paper focuses on observability, one of the open issues in High-Level test generation. Three different approximate metrics for taking observability into account during RT-leve...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
ATS
2003
IEEE
98views Hardware» more  ATS 2003»
13 years 10 months ago
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
ICCAD
2002
IEEE
116views Hardware» more  ICCAD 2002»
14 years 1 months ago
Conflict driven techniques for improving deterministic test pattern generation
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xiji...
DDECS
2008
IEEE
97views Hardware» more  DDECS 2008»
13 years 11 months ago
Incremental SAT Instance Generation for SAT-based ATPG
— Due to ever increasing design sizes more efficient tools for Automatic Test Pattern Generation (ATPG) are needed. Recently ATPG based on Boolean satisfiability (SAT) has been ...
Daniel Tille, Rolf Drechsler