207 search results - page 3 / 42 » RTL Processor Synthesis for Architecture Exploration and Imp... |
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
It is common wisdom that synthesizing hardware from higher-level descriptions than Verilog will incur a performance penalty. The case study here shows that this need not be the ca...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
The development of application specific instruction set processors comprises several design phases: architecture exploration, software tools design, system verification and design...
DAC
1998
ACM
13 years 9 months ago
1998
ACM
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...