4 search results - page 1 / 1 » RTL Test Point Insertion to Reduce Delay Test Volume |
VTS
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
ITC
2002
IEEE
13 years 10 months ago
2002
IEEE
Efficient production testing is frequently hampered because current digital circuits require test sets which are too large. These test sets can be reduced significantly by means...
TCAD
1998
13 years 5 months ago
1998
—Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are...
TVLSI
2002
13 years 5 months ago
2002
Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simp...