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» Rapid Resource-Constrained Hardware Performance Estimation
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RTCSA
2007
IEEE
13 years 11 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
EURODAC
1995
IEEE
117views VHDL» more  EURODAC 1995»
13 years 8 months ago
Performance-complexity analysis in hardware-software codesign for real-time systems
The paper presents an approach for performance and complexity analysis of hardware/software implementations for real-time systems on every stage of the partitioning. There are two...
Victor V. Toporkov
ISCAS
2003
IEEE
123views Hardware» more  ISCAS 2003»
13 years 10 months ago
Fast prototyping of reconfigurable architectures from a C program
Rapid evaluation and design space exploration at the algorithmic level are important issues in the design cycle. In this paper we propose an original area vs delay estimation meth...
Sebastien Bilavarn, Guy Gogniat, Jean Luc Philippe...
DATE
2002
IEEE
206views Hardware» more  DATE 2002»
13 years 9 months ago
Accurate Area and Delay Estimators for FPGAs
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
Anshuman Nayak, Malay Haldar, Alok N. Choudhary, P...
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
13 years 9 months ago
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
Jörg Henkel, Tony Givargis, Frank Vahid