29 search results - page 3 / 6 » Rapid estimation of power consumption for hybrid FPGAs |
SLIP
2009
ACM
14 years 4 days ago
2009
ACM
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant ove...
ASPDAC
2000
ACM
13 years 10 months ago
2000
ACM
Reducing power consumption has become a key goal for systemon-a-chip (SOC) designs. Fast and accurate power estimation is needed early in the design process, since power reduction...
CODES
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
DATE
2000
IEEE
13 years 10 months ago
2000
IEEE
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...