3 search results - page 1 / 1 » Realistic-Faults Mapping Scheme for the Fault Simulation of ... |
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
common use is the distinction into two (abstract) fault models: A new fault modelling scheme for integrated analogue general the "Single Hard Fault Model (SHFM)" and the ...
MICRO
2006
IEEE
13 years 4 months ago
2006
IEEE
Shrinking devices to the nanoscale, increasing integration densities, and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. Frequent oc...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than ...