4 search results - page 1 / 1 » Realization of Regular Ternary Logic Functions |
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
ISMVL
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper introduces the implementation of the Iterative Symmetry Indices Decomposition (ISID) for the synthesis of ternary threedimensional logic circuits. The synthesis of regu...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
In this paper, a new realization for logic functions, namely Reversible Programmable Logic Array (RPLA), has been proposed. The proposed realization has the advantage of regularit...
CCA
2009
Springer
13 years 11 months ago
2009
Springer
Abstract. In this paper we study a reducibility that has been introduced by Klaus Weihrauch or, more precisely, a natural extension of this reducibility for multi-valued functions ...