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CASES
2008
ACM
13 years 6 months ago
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
Houman Homayoun, Mohammad A. Makhzan, Alexander V....
ISCA
1996
IEEE
130views Hardware» more  ISCA 1996»
13 years 9 months ago
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
Mark Horowitz, Margaret Martonosi, Todd C. Mowry, ...
HICSS
2009
IEEE
177views Biometrics» more  HICSS 2009»
13 years 11 months ago
Intelligent Alarm Processing: From Data Intensive to Information Rich
The requirement for power system operators to respond more efficiently to the stressed power system conditions that may create large number of alarms asks fort advanced alarm proc...
Mladen Kezunovic, Yufan Guan
LCTRTS
2000
Springer
13 years 8 months ago
Approximation of Worst-Case Execution Time for Preemptive Multitasking Systems
The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and su...
Matteo Corti, Roberto Brega, Thomas R. Gross
INFFUS
2007
88views more  INFFUS 2007»
13 years 4 months ago
A progressive query language and interactive reasoner for information fusion support
Previous approaches in query processing do not consider queries to automatically combine results obtained from different information sources, i.e. they do not support information...
Shi-Kuo Chang, Erland Jungert, Xin Li