18 search results - page 2 / 4 » Reducing Communication Latency with Path Multiplexing in Opt... |
3DIC
2009
IEEE
13 years 8 months ago
2009
IEEE
Abstract— Networks-on-chip (NoC) is emerging as a key onchip communication architecture for multiprocessor systemson-chip (MPSoC). In traditional electronic NoCs, high bandwidth ...
ISCA
1992
IEEE
13 years 9 months ago
1992
IEEE
As multiprocessor sizes scale and computer architects turn to interconnection networks with non-uniform communication latencies, the lure of exploiting communication locality to i...
TC
2008
13 years 5 months ago
2008
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...
TVLSI
2010
12 years 11 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
ASPDAC
2012
ACM
12 years 24 days ago
2012
ACM
Abstract— Integrating optical interconnects into the nextgeneration multi-/many-core architecture has been considered a viable solution to addressing the limitations in throughpu...